Name
Abstract | ||
|---|---|---|
Because of the similarities in the algorithm it is quite common to implement division and square root in the same unit. The purpose of this work is to implement a low-power combined radix-4 division and square root floating-point double precision unit and to compare its performance and energy consumption with a radix-4 division only unit. Previous work has been done on reducing the energy dissipated in a divider. Here we apply the same techniques to the combined division and square root unit and consider modifications and tradeoffs. Results show that the energy dissipation for the combined division/square root unit can be reduced by about 35% without affecting the latency and an additional 20% reduction can be obtained using a dual voltage. Moreover the unit is 5% slower than a divider and its energy dissipation is 15% higher |
Year | DOI | Venue |
|---|---|---|
1999 | 10.1109/ICCD.1999.808431 | ICCD |
Keywords | Field | DocType |
previous work,radix-4 division,combined division,latency,dividing circuits,square root,low-power radix-4,division,floating-point double precision unit,energy dissipation,energy consumption,dual voltage,performance,low-power radix-4 combined division,square root unit,floating point arithmetic,voltage,computational modeling,floating point,power dissipation | Floating point,Computer science,Dissipation,Control theory,Double-precision floating-point format,Parallel computing,Voltage,Electronic engineering,Radix,Dividing circuits,Square root,Energy consumption | Conference |
ISSN | ISBN | Citations |
1063-6404 | 0-7695-0406-X | 6 |
PageRank | References | Authors |
0.65 | 8 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Nannarelli, A. | 1 | 6 | 0.65 |
| Lang, T. | 2 | 38 | 4.02 |