Name
Abstract | ||
|---|---|---|
Ensuring a high manufacturing test quality of an integrated electronic circuit mandates the application of a large volume test set. Even if the test data can be fit into the memory of an external tester, the consequent increase in test application time reflects into elevated production costs. Test data compression solutions have been proposed to address the test time and data volume problem by storing and delivering the test data in a compressed format, and subsequently by expanding the data on-chip. In this paper, we propose a scan cell positioning methodology that accompanies a compression technique in order to boost the compression ratio, and squash the test data even further. While we present the application of the proposed approach in conjunction with the fan-out based decompression architecture, this approach can be extended for application along with other compression solutions as well. The experimental results also confirm the compression enhancement of the proposed methodology. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1007/s11390-009-9268-6 | J. Comput. Sci. Technol. |
Keywords | Field | DocType |
cell positioning,scan architecture design,test data,compression enhancement,scan cell reordering,test data compression,high manufacturing test quality,scan-based testing,data volume problem,compression ratio,test application time,test time,fan-out network,test data compression solution,data on-chip,large volume test set,chip | Compression (physics),Computer science,Simulation,Compression ratio,Test data,Boosting (machine learning),Electronic circuit,Test compression,Fan-out,Test set | Journal |
Volume | Issue | ISSN |
24 | 5 | 1860-4749 |
Citations | PageRank | References |
0 | 0.34 | 13 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ozgur Sinanoglu | 1 | 971 | 79.32 |
| Mohammed Almulla | 2 | 147 | 20.60 |
| Noora A. Shunaiber | 3 | 0 | 0.34 |
| Alex Orailoglu | 4 | 1449 | 151.01 |