Name
Abstract | ||
|---|---|---|
Two technological trends we notice in the current day systems is the march towards many core systems and greater focus on power efficiency. The increase in core counts would result in smaller caches-per-compute node and greater reliance on exposing task-level parallelism in applications. However, this would potentially increase the amount of data that moves within and between the different tasks and hence, the related power costs. This will pose a new burden on the already power-constrained current day systems. The situation would only get worse as we go forward because the power consumed by the wires is not scaling down much with each technology generation, but the amount of data that these wires move is increasing per generation. This paper addresses this concern by identifying the memory access patterns that accounts for much of the data movement and designing processor extensions, Apes to support them. These processor extensions are placed closer to the cache structures, rather than the core pipeline, to reduce the data movement and improve compute-data co-location. We show that by doing this we are able to reduce a task's memory accesses by ~2.5×, data movement by 4× and cache miss rate by 40% for a wide range of applications. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1145/2492408.2492412 | MSPC@PLDI |
Keywords | Field | DocType |
related power cost,accelerator processor extension,power efficiency,core pipeline,greater focus,core count,data-compute co-location,cache structure,current day system,processor extension,data movement,core system | Electrical efficiency,Computer science,Cache,Parallel computing,Notice,Cache miss,Computer engineering,Scaling | Conference |
Citations | PageRank | References |
0 | 0.34 | 11 |
Authors | ||
1 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ganesh Venkatesh | 1 | 274 | 17.97 |