Paper Info
Title
AER spike-processing filter simulator: Implementation of an AER simulator based on cellular automata
Abstract
Spike-based systems are neuro-inspired circuits implementations traditionally used for sensory systems or sensor signal processing. Address-Event-Representation (AER) is a neuromorphic communication protocol for transferring asynchronous events between VLSI spike-based chips. These neuro-inspired implementations allow developing complex, multilayer, multichip neuromorphic systems and have been used to design sensor chips, such as retinas and cochlea, processing chips, e.g. filters, and learning chips. Furthermore, Cellular Automata (CA) is a bio-inspired processing model for problem solving. This approach divides the processing synchronous cells which change their states at the same time in order to get the solution. This paper presents a software simulator able to gather several spike-based elements into the same workspace in order to test a CA architecture based on AER before a hardware implementation. Furthermore this simulator produces VHDL for testing the AER-CA into the FPGA of the USB-AER AER-tool.
Year
Venue
Keywords
2011
Signal Processing and Multimedia Applications
cellular automata,field programmable gate arrays,hardware description languages,neural chips,AER spike-processing filter simulator,AER-CA testing,CA,FPGA,VHDL,VLSI spike-based chips,Verilog hardware description language,address-event-representation,asynchronous events,bio-inspired processing model,cellular automata,field programmable gate array,multichip neuromorphic systems,neuro-inspired circuits,neuromorphic communication protocol,processing chips,sensor chips design,sensor signal processing,sensory systems,software simulator,spike-based elements,spike-based systems,synchronous cells processing,very large scale integrated circuits,Address-event-representation,Cellular automata,Fpga,Image filtering,Neuro-inspired,Spiking neurons,Usb-aer,Vhdl
Field
DocType
Citations 
Cellular automaton,Asynchronous communication,Signal processing,Computer science,Simulation,Neuromorphic engineering,Field-programmable gate array,VHDL,Very-large-scale integration,Hardware description language,Embedded system
Conference
0
PageRank 
References 
Authors
0.34
0
8
Name
Order
Citations
PageRank
Manuel Corona-perez113411.36
Alejandro Linares-barranco247353.18
Angel Jiménez-fernandez39620.53
Antón Civit413519.32
Gabriel Jiménez58710.18
Rivas-Perez, M.600.34
Linares-Barranco, A.71449.02
Jimenez-Fernandez, A.800.68