Name
Abstract | ||
|---|---|---|
Discrete wavelet transform has been incorporated as part of the JPEG2000 image compression standard and is being deployed in various portable consumer products. This raises the interest in low-power design of DWT processor. This paper presents a low-power implementation of a 2-D biorthogonal DWT processor that uses residue number arithmetic. By incorporating a 4-stage pipeline, the processor is able to sustain the same throughput with a lower supply voltage. Hardware complexity reduction and utilization improvement are achieved by resource sharing. Our implementation results show that the design is able to fit into a 1,000,000-gate FPGA device. |
Year | Venue | Keywords |
|---|---|---|
2004 | ESA'04 & VLSI'04, PROCEEDINGS | discrete wavelet transform |
Field | DocType | Citations |
Lifting scheme,Computer science,Second-generation wavelet transform,Discrete wavelet transform,Discrete Hartley transform,Stationary wavelet transform,Computer hardware,Wavelet packet decomposition,Wavelet transform,Wavelet | Conference | 0 |
PageRank | References | Authors |
0.34 | 2 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yong Liu | 1 | 146 | 34.31 |
| Edmund Ming-Kit Lai | 2 | 120 | 58.89 |
| A. Benjamin Premkumar | 3 | 91 | 14.80 |
| Damu Radhakrishnan | 4 | 21 | 5.39 |