Name
Title | ||
|---|---|---|
A 1-GS/s 6-Bit Two-Channel Two-Step ADC in 0.13-<formula formulatype="inline"><tex Notation="TeX">$\mu$</tex></formula>m CMOS |
Abstract | ||
|---|---|---|
In this paper, a 6-bit 1-GS/s 49 mW two-channel two-step analog-to-digital converter (ADC) without calibration is implemented in 0.13- mum CMOS process. The proposed multiplying digital-to-analog converter (MDAC) processes the analog signal with two clock periods for one conversion: half for sampling, half for coarse ADC (CADC) resolving, and one for residue amplification. A self-timing technique ... |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/JSSC.2009.2032258 | IEEE Journal of Solid-State Circuits |
Keywords | DocType | Volume |
Analog-digital conversion,Calibration,CMOS process,Digital-analog conversion,Signal processing,Clocks,Image converters,Signal sampling,Signal resolution,Voltage | Journal | 44 |
Issue | ISSN | Citations |
11 | 0018-9200 | 7 |
PageRank | References | Authors |
0.91 | 5 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hung-Wei Chen | 1 | 151 | 16.28 |
| I-Ching Chen | 2 | 21 | 5.31 |
| Huan-Chieh Tseng | 3 | 8 | 1.29 |
| Hsin-shu Chen | 4 | 93 | 16.12 |