Name
Title | ||
|---|---|---|
A 6T-SRAM With a Post-Process Electron Injection Scheme That Pinpoints and Simultaneously Repairs Disturb Fails for 57% Less Read Delay and 31% Less Read Energy. |
Abstract | ||
|---|---|---|
A post-process carrier injection scheme for 6T-SRAM is proposed. The proposed scheme pinpoints and simultaneously repairs only cells that have low read disturb margin by injecting electrons to the strong pass gate transistor. Compared with the conventional electron injection scheme that injects electrons to either side of the pass gate transistor of all cells, the proposed scheme achieves 57% less... |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/JSSC.2013.2262735 | IEEE Journal of Solid-State Circuits |
Keywords | Field | DocType |
Transistors,Maintenance engineering,Arrays,Logic gates,SRAM cells,Delays | Computer science,% area reduction,Electron injection,Electronic engineering,Static random-access memory,Cmos process,Pass gate,Transistor,Electron | Journal |
Volume | Issue | ISSN |
48 | 9 | 0018-9200 |
Citations | PageRank | References |
0 | 0.34 | 15 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kousuke Miyaji | 1 | 59 | 9.73 |
| Toshi-kazu Suzuki | 2 | 73 | 11.00 |
| Shinji Miyano | 3 | 85 | 12.63 |
| Ken Takeuchi | 4 | 15 | 2.93 |