Paper Info
Title
Power and area optimization for multiple restricted multiplication
Abstract
This paper presents a design and optimization technique for the multiple restricted multiplication problem [N. Sidahao, G. A. Constantinides, and F. Y. Cheung (2004)]. This refers to a situation where a single variable is multiplied by several coefficients which, while not constant, are drawn from a finite set of constants that change with time. The approach exploits dedicated registers in FPGA architecture for further time-step based optimization over previous approaches [N. Sidahao, G. A. Constantinides, and F. Y. Cheung. S. S. Demirsoy, A. G. Dempster, and I. Kale (2003)]. It is also combined with an effective technique, based on high-level power modelling, for power optimization. The problem is formulated into an integer linear program for finding solutions to the minimum-costs. The new approach results up to 22% area saving compared to the optimal non-register approach in [N. Sidahao, G. A. Constantinides, and F. Y. Cheung (2004)], and 80% of all results also show 21%-48% power savings.
Year
DOI
Venue
2005
10.1109/FPL.2005.1515708
FPL
Keywords
Field
DocType
fpga architecture,integer linear program,area optimization,power optimization,time-step based optimization,high-level power modelling,multiplying circuits,integer programming,circuit optimisation,linear programming,multiple restricted multiplication problem,field programmable gate arrays,optimization technique
Integer,Finite set,Power optimization,Computer science,Parallel computing,Field-programmable gate array,Multiplication,Integer programming,Linear programming,Fpga architecture
Conference
ISBN
Citations 
PageRank 
0-7803-9362-7
0
0.34
References 
Authors
8
3
Name
Order
Citations
PageRank
Nalin Sidahao141.49
George A. Constantinides21391160.26
Peter Y. K. Cheung31720208.45