Name
Abstract | ||
|---|---|---|
In this paper, a new cryptography system (CS) is proposed and its VLSI architecture is designed and verified. The new system performs both random position permutation and random value transformation. The input data is processed by the swap and XOR/XNOR functions under the control of a binary sequence from a chaotic system. The scheme is analyzed and simulated by MATLAB to be high security. In order to maintain the requirement of real-time, the VLSI architecture with low hardware cost, high computing speeds, high modularity, and regularity is designed and implemented respectively with Altera FPGA and Avanti cell-library. According to the simulation result, the throughput rates of the proposed design with the two implementations are larger than 0.64 and 2.74 Gbps. Hence the proposed new cryptography system is strongly suitable for most of real-time video and audio applications. |
Year | DOI | Venue |
|---|---|---|
2003 | 10.1016/S1383-7621(03)00087-0 | Journal of Systems Architecture |
Keywords | Field | DocType |
Cryptography system,Chaotic system,VLSI design and verification | MATLAB,XNOR gate,Computer science,Cryptography,Parallel computing,Field-programmable gate array,Pseudorandom binary sequence,Real-time computing,Throughput,Chaotic,Very-large-scale integration | Journal |
Volume | Issue | ISSN |
49 | 7 | 1383-7621 |
Citations | PageRank | References |
21 | 2.40 | 8 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hun-Chen Chen | 1 | 108 | 11.20 |
| Jui-Cheng Yen | 2 | 266 | 23.97 |