Paper Info
Title
Thirty Two-Stage CMOS TDI Image Sensor With On-Chip Analog Accumulator
Abstract
This brief presents a 32-stage CMOS time delay integration image sensor with on-chip column parallel analog accumulator. Temporal oversampling technique is applied in the sensor to realize synchronous signal capturing. A column parallel analog accumulator with layout size of 0.09 ${\rm mm}^{2}$ is integrated at both sides of pixel array. Through adopting input-offset storing technique, a column fixed pattern noise because of the amplifier's offset variations is reduced by the accumulator. The accumulator also acts as a pixel noise canceller. The fabricated chip in 0.18-$\mu{\rm m}$ one-poly four-metal 1.8/3.3-V CMOS technology achieves the maximum line rate of 3875 lines/s. The measured signal-to-noise ratio of the fabricated sensor is improved on average by 11.9 dB at 16 stages and 14.2 dB at 32 stages. The presented sensor is suitable for application in low illumination, high scanning speed, and remote sensing systems.
Year
DOI
Venue
2014
10.1109/TVLSI.2013.2256809
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Keywords
Field
DocType
cmos image sensors,input offset storing technique,pixel array,synchronous signal capturing,readout circuits,signal sampling,analogue-digital conversion,readout electronics,on chip column parallel analog accumulator,signal-to-noise ratio (snr),size 0.18 mum,voltage 3.3 v,temporal oversampling technique,cmos tdi image sensor,analog accumulator,column fixed pattern noise,pixel noise canceller,time delay integration (tdi),time delay integration,voltage 1.8 v
Fixed-pattern noise,Oversampling,Image sensor,Computer science,Chip,CMOS,Electronic engineering,Pixel,Computer hardware,Accumulator (structured product),Amplifier
Journal
Volume
Issue
ISSN
22
4
1063-8210
Citations 
PageRank 
References 
9
1.07
4
Authors
4
Name
Order
Citations
PageRank
Kaiming Nie1358.77
Suying Yao2479.18
Jiangtao Xu37418.98
Jing Gao4244.95