Paper Info
Title
Parallel morphological image processing with an opto-electronic VLSI array processor
Abstract
A parallel morphological image processor (MIP) has been developed onto a full-custom optoelectronic VLSI design by combining a two-dimensional fine-grain parallel array architecture with on-chip focal-plane photodetectors and transmitters. The optical input/output (I/O) array processor performs morphological functions on the optodetected binary image with a programmable structuring element of any size. A language called MIPL is defined for parallel morphological image processing and fully supported by the MIP hardware. An 8*8 array processor prototype chip has been designed in 1.6-mm*1.6-mm silicon area using the MOSIS 2- mu m CMOS process.<>
Year
DOI
Venue
1993
10.1109/ICASSP.1993.319142
ICASSP
Keywords
Field
DocType
cmos integrated circuits,programmable structuring element,mipl,array processor prototype chip,parallel architectures,fine-grain parallel array architecture,parallel morphological image processor,opto-detected binary image,morphological function,mathematical morphology,prototype chip,digital signal processing chips,parallel languages,on-chip focal-plane photodetectors,2-dimensional fine-grain parallel array,language,vlsi,mm silicon area,vlsi design,opto-electronic vlsi array processor,mip hardware,parallel morphological image processing,o array processor,cmos,integrated optoelectronics,image processing equipment,binary image,very large scale integration,workstations,chip,image processing,hardware,input output,photodetectors
Computer science,Binary image,Image processing,Image processor,Structuring element,Artificial intelligence,Computer hardware,Very-large-scale integration,Pattern recognition,Parallel computing,Chip,Vector processor,Parallel array
Conference
Volume
ISSN
Citations 
1
1520-6149
2
PageRank 
References 
Authors
0.67
0
5
Name
Order
Citations
PageRank
Wai-Chi Fang129952.98
Timothy Shaw220.67
Jeffrey Yu322.02
Brian Lau4154.00
Yi-Chun Lin520.67