Name
Abstract | ||
|---|---|---|
With rapid strides in Semiconductor processing technologies, the density of transistors on the die is increasing in line with Moore’s law which in turn is increasing the complexity of the whole SoC design. With manufacturing yield and time-to-market schedules crucial for a SoC, it is important to select verification and analysis solutions that offer best possible performance, while minimizing iteration time and data volume. With the advent of cutting edge technology applications like set top boxes, HDTV, an increasingly evident need has been that of incorporating the SoC the whole system - on a single silicon i.e., Silicon On Chip (SoC) using standard IP-Cores. In an IP-Core based SoC design, a streamlined verification and analysis flow can contribute significantly to the success of a product. A strategy is devised for a more streamlined approach in IP-core based SoC verification which helps in smooth transition from design to chip tape-out stage. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/ISQED.2008.73 | ISQED |
Keywords | Field | DocType |
analysis flow,streamlined verification,whole soc design,whole system,chip tape-out stage,semiconductor processing technology,analysis solution,streamlined approach,soc verification,soc design,integrated circuit design,routing,hardware,soc,software testing,system on chip,moore law,silicon,chip,layout,moore s law,smooth transition,verification,system on a chip,system testing | System on a chip,High-definition television,System testing,Computer science,Electronic engineering,Chip,Integrated circuit design,Schedule,Transistor,Moore's law,Embedded system | Conference |
Citations | PageRank | References |
3 | 0.40 | 1 |
Authors | ||
1 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Anil Deshpande | 1 | 3 | 0.40 |