Paper Info
Title
A ROM-less direct digital frequency synthesizer based on 16-segment parabolic polynomial interpolation
Abstract
This paper presents a novel architecture for direct digital frequency synthesizer (DDFS) based on a modified par- abolic polynomial interpolation method. A 16-segment parabolic polynomial interpolation is adopted to replace conventional ROM-based phase-to-amplitude conversion method. Besides, the proposed parabolic polynomial interpolation is realized in a multiplier-less fashion such that the speed can be significantly improved. The proposed DDFS is implemented in a standard 0.13 µm cell-based technology. The maximum clock rate is 227 MHz, and the core area is 0.25 mm2. The simulation result shows that the spurious free dynamic range (SFDR) is 117 dBc. I. INTRODUCTION
Year
DOI
Venue
2008
10.1109/ICECS.2008.4675029
ICECS
Keywords
Field
DocType
spurious free dynamic range,interpolation,maximum clock rate,direct digital synthesis,phase-amplitude conversion,16-segment parabolic polynomial interpolation,size 0.13 mum,rom-less direct digital frequency synthesizer,read only memory,frequency control,polynomials,polynomial interpolation
Polynomial,Polynomial interpolation,Computer science,Interpolation,Spurious-free dynamic range,Electronic engineering,Automatic frequency control,Control engineering,Direct digital synthesizer,Clock rate,Parabola
Conference
ISBN
Citations 
PageRank 
978-1-4244-2182-4
1
0.41
References 
Authors
2
3
Name
Order
Citations
PageRank
Jian-Ming Huang1668.49
Chia-Chuan Lee210.74
Chua-chin Wang3474107.39