Name
Abstract | ||
|---|---|---|
In this paper a twou0027s complement parameterized multiplier/inner-product unit cell is presented. It can be used as a library element when a methodology for Design with Reusability (DwR) is applied. The multiplicand and multiplier operands can be of any size. The cell code is written as VHDL suited for the Synopsys high-level synthesis tool. |
Year | DOI | Venue |
|---|---|---|
1999 | 10.1109/EURMIC.1999.794468 | EUROMICRO |
Keywords | Field | DocType |
hardware description languages,vhdl,signal generators,algorithm design and analysis,inner product,multiplicand,high level synthesis,digital signal processing,arithmetic,decision support systems,read only memory | Read-only memory,Computer architecture,Algorithm design,Computer science,High-level synthesis,Operand,Multiplier (economics),VHDL,Computer hardware,Reusability,Hardware description language | Conference |
Volume | Citations | PageRank |
1 | 2 | 0.54 |
References | Authors | |
2 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| M. A. Sacristán | 1 | 3 | 0.98 |
| María Victoria Rodellar Biarge | 2 | 44 | 13.67 |
| A. Diaz | 3 | 2 | 0.88 |
| V. Garcia | 4 | 5 | 1.80 |
| Pedro Gómez Vilda | 5 | 289 | 52.48 |