Name
Title | ||
|---|---|---|
Predicting the Worst-Case Execution Time of the Concurrent Execution of Instructions and Cycle-Stealing DMA I/O Operations |
Abstract | ||
|---|---|---|
This paper describes an efficient algorithm which gives a bound on the worst-case execution times of the concurrent execution of CPU instructions and cycle-stealing DMA I/O operations. Simulations of several programs were conducted to evaluate this algorithm. Compared with the traditional pessimistic approach, the bound on the worst-case execution time produced by the algorithm is significantly tighter. For a sample program that multiplies two matrices while the I/O bus is fully utilized, our algorithm achieves a 39% improvement in the accuracy of the prediction. |
Year | Venue | Keywords |
|---|---|---|
1995 | SIGPLAN NOTICES | worst case execution time |
Field | DocType | Volume |
Cycle stealing,Worst-case execution time,Computer science,Parallel computing,Input/output | Conference | 30 |
Issue | ISSN | Citations |
11 | 0362-1340 | 8 |
PageRank | References | Authors |
0.84 | 5 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Taiyi Huang | 1 | 256 | 33.43 |
| Jane W.-S. Liu | 2 | 1399 | 337.97 |