Name
Title | ||
|---|---|---|
Coding For Jointly Optimizing Energy And Peak Current In Deep Sub-Micron Vlsi Interconnects |
Abstract | ||
|---|---|---|
In deep sub-micron processes, on-chip interconnect is becoming the delay bottleneck and predominant source of power consumption. Simultaneous switching of large buses pose a great challenge on peak current as well. In this paper, we present a novel bus coding technique, based on transition pattern codes (TPC), to perform joint optimization. A TPC scheme has been constructed employing a joint cost function on energy and peak current. The encoder and decoder of the code has been synthesized using a commercial 28nm process and the power, delay and area overhead has been evaluated. HSPICE simulations in 28nm show up to 70% reduction in peak current and 15% reduction in energy consumption compared to an uncoded bus. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/ISCAS.2012.6271974 | 2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012) |
Keywords | Field | DocType |
very large scale integration,encoding,cost function,vlsi,low power electronics,decoding | Bottleneck,Computer science,Electronic engineering,Encoder,Decoding methods,Interconnection,Very-large-scale integration,Energy consumption,Encoding (memory),Low-power electronics | Conference |
ISSN | Citations | PageRank |
0271-4302 | 0 | 0.34 |
References | Authors | |
7 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Eric P. Kim | 1 | 62 | 6.67 |
| Hun-Seok Kim | 2 | 294 | 27.15 |
| M. Goel | 3 | 231 | 27.01 |