Paper Info
Title
High Area-Efficient DC-DC Converter With High Reliability Using Time-Mode Miller Compensation (TMMC)
Abstract
This paper presents a novel on-chip compensation scheme, the Time-Mode Miller Compensation (TMMC), for DC-DC converter in which the compensation components are integrated on-chip. Using this proposed scheme, the DC-DC converter is stably compensated and insensitive to process variations, with significantly small compensation components ( 1 pF and 80 kΩ in this work) consuming very small silicon area owing to the characteristic of the TMMC. The small compensation components make the chip size small, with 0.12 mm2 of core area (w/o power transistors) using 0.18 μm I/O process. This core size is as small as that of the digital DC-DC converters implemented with less than sub-50 nm process. The measurement result shows that the maximum power efficiency of 90.6% is obtained at the load current of 220 mA with the switching frequency of 1.15 MHz when the input and the output voltages are 3.3 V and 2 V, respectively.
Year
DOI
Venue
2013
10.1109/JSSC.2013.2272845
J. Solid-State Circuits
Keywords
Field
DocType
process variation,switching convertors,maximum power efficiency,dc-dc power conversion,dc-dc power convertors,current 220 ma,on-chip compensation scheme,voltage 3.3 v,miller compensation,frequency 1.15 mhz,load current,size 0.18 mum,reliability,tmmc,time-mode miller compensation,compensation,i-o process,compensation component,cost efficiency,voltage 2 v,on-chip compensation,high area-efficient dc-dc converter,switching frequency
Computer science,Power semiconductor device,Voltage,Electronic engineering,Converters,Chip size,Dc dc converter,Maximum power principle,Electronic circuit,Electrical engineering,Silicon
Journal
Volume
Issue
ISSN
48
10
0018-9200
Citations 
PageRank 
References 
5
0.81
8
Authors
7
Name
Order
Citations
PageRank
Sung-Wan Hong15012.32
Tae-Hwang Kong2397.11
Sang-Hui Park38411.56
Changbyung Park4468.41
Seungchul Jung55011.03
Sungwoo Lee66114.50
Gyu-Hyeong Cho740176.39