Name
Title | ||
|---|---|---|
Decomposing specifications with concurrent outputs to resolve state coding conflicts in asynchronous logic synthesis |
Abstract | ||
|---|---|---|
Synthesis of asynchronous logic using the tool Petrify requires a state graph with a complete state coding. It is common for specifications to exhibit concurrent outputs, but Petrify is sometimes unable to resolve the state coding conflicts that arise as a result, and hence cannot synthesise a circuit. A pair of decomposition heuristics (expressed in the language of Delay-Insensitive Sequential Processes) are given that helps one to obtain a synthesisable specification. The second heuristic has been successfully applied to a set of nine benchmarks to obtain significant reductions both in area and in synthesis time, compared with synthesis performed on the original specifications. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1145/996566.996788 | San Diego, CA, USA |
Keywords | Field | DocType |
asynchronous logic,significant reduction,tool petrify,concurrent output,synthesis time,state graph,complete state coding,original specification,decomposition heuristics,delay-insensitive sequential processes,decomposing specification,asynchronous logic synthesis,hardware,petri nets,automatic control,logic synthesis,logic design,very large scale integration | Logic synthesis,Heuristic,Sequential logic,Logic optimization,Computer science,Theoretical computer science,Real-time computing,Electronic engineering,Heuristics,Register-transfer level,Logic family,Asynchronous circuit | Conference |
ISSN | ISBN | Citations |
0738-100X | 1-58113-828-8 | 4 |
PageRank | References | Authors |
0.42 | 9 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hemangee K. Kapoor | 1 | 99 | 28.66 |
| Mark B. Josephs | 2 | 302 | 35.24 |