Name
Abstract | ||
|---|---|---|
The quality of at-speed testing is being severely challenged by the problem that an inter-clock logic block existing between two synchronous clocks is not efficiently tested or totally ignored due to complex test control. This paper addresses the problem with a novel inter-clock at-speed test control scheme, featuring a compact and robust on-chip inter-clock enable generator design. The new scheme can generate inter-clock at-speed test clocks from PLLs, and is feasible for both ATE-based scan testing and logic BIST Successful applications to industrial circuits have proven its effectiveness in improving the quality of at-speed testing. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/TEST.2006.297641 | 2006 IEEE INTERNATIONAL TEST CONFERENCE, VOLS 1 AND 2 |
Keywords | Field | DocType |
chip,phase locked loops,automatic test equipment | Automatic test pattern generation,Automatic test equipment,Computer science,Scan chain,Electronic engineering,Real-time computing,Logic block,Test compression,Electronic circuit,AND gate,Built-in self-test,Embedded system | Conference |
ISSN | Citations | PageRank |
1089-3539 | 8 | 0.57 |
References | Authors | |
17 | 6 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hiroshi Furukawa | 1 | 211 | 31.32 |
| Xiaoqing Wen | 2 | 790 | 77.12 |
| Laung-terng Wang | 3 | 601 | 44.22 |
| Boryau Sheu | 4 | 46 | 4.85 |
| Zhigang Jiang | 5 | 85 | 20.12 |
| Shianling Wu | 6 | 165 | 26.85 |