Name
Abstract | ||
|---|---|---|
Image processing operations require that an image or partial image be stored in a memory system that permits access to p × q, 1 × pq, and/or pq × 1 subarrays of an image array where p and q are design parameters. |
Year | DOI | Venue |
|---|---|---|
1986 | 10.1109/TC.1986.1676813 | IEEE Trans. Computers |
Keywords | Field | DocType |
address routing circuit,image processing,design parameter,image processing operation,data routing circuitry,address calculating circuitry,image array,efficient memory system,partial image,memory system,registers,circuits,routing,statistics,shape,hardware,computer science | Access time,Computer science,Parallel computing,Circuit design,Image processing | Journal |
Volume | Issue | ISSN |
C | 7 | 0018-9340 |
Citations | PageRank | References |
24 | 3.06 | 5 |
Authors | ||
1 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jong Won Park | 1 | 74 | 9.56 |