Name
Abstract | ||
|---|---|---|
This paper considers a general parallel buffered packet switch (PBPS) architecture which is based on multiple packet switches operating independently and in parallel. A load-balancing mechanism is used at each input to distribute the traffic to the parallel switches. The buffer structure of each of the parallel packet switches is based on either a dedicated, a shared, or a buffered-crosspoint outp... |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/TCOMM.2007.892460 | IEEE Transactions on Communications |
Keywords | Field | DocType |
Packet switching,Switches,Communication switching,Very large scale integration,Bandwidth,Out of order,System recovery,Delay,Switching systems | Multipath propagation,Computer science,Load balancing (computing),Deadlock,Network packet,Computer network,Queueing theory,Head-of-line blocking,Packet switching,Out-of-order execution | Journal |
Volume | Issue | ISSN |
55 | 3 | 0090-6778 |
Citations | PageRank | References |
0 | 0.34 | 9 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| I. Iliadis | 1 | 269 | 26.31 |
| Wolfgang E. Denzel | 2 | 212 | 14.56 |