Paper Info
Title
CAST: A page-level FTL with compact address mapping and parallel data blocks
Abstract
NAND flash memory based Solid State Drive (SSD) is increasingly popular as one of the major non-volatile storage devices. Due to the superior performance and energy efficiency properties, it becomes an important complimentary device between the main memory and the traditional mechanical Hard Disk Drive (HDD). It is also anticipated to substitute HDD as the mainstream secondary storage. Today, flash memory is widely used in embedded systems, hand-held devices, personal computers and even enterprise computer systems. To access the data on the flash, a software component called Flash Translation Layer (FTL) has to be applied to convert the file system logical address into the corresponding physical address. FTL has great impacts on the system overall performance. Numerous FTL algorithms have been proposed in the past decade. DFTL is one of the most popular page-level address mapping FTL algorithms. It has been considered to have the best flexibility. However, it has extra mapping information I/O overhead and cannot always achieve the optimal performance. In this paper, we propose CAST, a novel and efficient pagelevel FTL algorithm to relieve this issue. CAST reserves a small portion of embedded SRAM to cache most recently accessed logical-physical address mapping information. Unlike DFTL, we use a compact packing methodology. Consecutive logical-physical page mapping information is represented with only a single entry. Thus, more address mapping information can be maintained in the caching table, and the cache hit rates can be increased. To improve the garbage collection efficiency, CAST maintains multiple current data blocks simultaneously. When a new data write request comes, the system can select an appropriate one to conduct the process based on the request issuer and/or logical address information. Our simulation results show that CAST outperforms DFTL under various workloads and it can reduce the number of erase operations and decrease the I/O response time sign- ficantly.
Year
DOI
Venue
2012
10.1109/PCCC.2012.6407747
IPCCC
Keywords
Field
DocType
nand circuits,demand-based ftl (dftl),parallel processing,page level ftl,software component,ssd,hand-held devices,parallel data blocks,cache storage,singlelevel cell (slc),nand flash memory,solid state drive,sram chips,disc drives,cast,solid-state drive (ssd),multi-level cell (mlc),enterprise computer systems,hard disk drive,sram,ftl,compact address mapping,flash translatio layer (ftl),flash translation layer,embedded systems,nonvolatile storage devices,hdd,hard discs,flash memories,personal computers
File system,Flash file system,Flash memory,Logical address,Physical address,Cache,Computer science,Solid-state drive,Operating system,Embedded system,Auxiliary memory
Conference
ISSN
ISBN
Citations 
1097-2641
978-1-4673-4881-2
10
PageRank 
References 
Authors
0.52
23
3
Name
Order
Citations
PageRank
Zhiyong Xu115615.97
Ruixuan Li240569.47
Z. Chen33443271.62