Name
Abstract | ||
|---|---|---|
This paper presents a 2GS/s 10-bit CMOS digital-to-analog converter (DAC). This DAC consists of a unit current-cell matrix for 6MSBs and another unit current-cell matrix for 4LSBs, trading off between the precision and size of the chip. The Current Mode Logic (CML) is used to ensure high speed, and a double Centro-symmetric current matrix is designed by the Q(2) random walk strategy in order to ensure the linearity of the DAC. The DAC occupies 2.2 x 2.2 mm2 of die area, and consumes 790mw at a single 3.3V power supply. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/ISCAS.2007.377991 | 2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11 |
Keywords | Field | DocType |
linearity,random walk,communication system,cmos technology,high resolution,logic design,direct digital synthesis,logic circuits,local oscillator,chip,signal processing,arbitrary waveform generator,decoding | Logic synthesis,Logic gate,Computer science,Matrix (mathematics),Linearity,CMOS,Chip,Electronic engineering,Digital-to-analog converter,Current-mode logic,Electrical engineering | Conference |
ISSN | Citations | PageRank |
0271-4302 | 2 | 0.52 |
References | Authors | |
4 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ling Yuan | 1 | 3 | 0.90 |
| Weining Ni | 2 | 9 | 1.85 |
| Yin Shi | 3 | 2 | 0.52 |
| Foster F. Dai | 4 | 20 | 6.51 |