Name
Abstract | ||
|---|---|---|
In this paper, the technological bricks specifically developed for 3D integration of a set top box demonstrator will be presented. The integration flow was based on the 45 nm technology top chip stacked on a 130 run technology active bottom wafer [1]. This flow needed to develop specific wafer level packaging technologies such as:Top chip & bottom chip interconnectionsHigh aspect ratio TSV included into the bottom waferBackside interconnections for subsequent packaging stepTemporary bonding and debonding of bottom waferTop chip stacking on bottom waferThe complete process flow will be presented. Then, a technical interconnections step. Finally, the electrical results achieved on demonstrator will be discussed. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/3DIC.2009.5306561 | 2009 IEEE INTERNATIONAL CONFERENCE ON 3D SYSTEMS INTEGRATION |
Keywords | Field | DocType |
Trough Silicon Vias (TSV), Wafer level Packaging, Stacking, back side connections | Wafer,Embedded Wafer Level Ball Grid Array,Wafer-level packaging,Mechanical engineering,Chip,Electronic engineering,Wafer testing,Engineering,Die preparation,Stacking,Wafer backgrinding | Conference |
ISSN | Citations | PageRank |
2164-0157 | 3 | 0.43 |
References | Authors | |
0 | 11 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| D. Henry | 1 | 20 | 2.37 |
| Séverine Cheramy | 2 | 22 | 4.74 |
| Jean Charbonnier | 3 | 3 | 0.43 |
| Pascal Chausse | 4 | 3 | 1.45 |
| Muriel Neyret | 5 | 3 | 0.43 |
| Cathy Brunet-Manquat | 6 | 3 | 0.43 |
| Sophie Verrun | 7 | 3 | 0.43 |
| Nicolas Sillon | 8 | 5 | 1.77 |
| Laurent Bonnot | 9 | 3 | 0.43 |
| X. Gagnard | 10 | 3 | 1.11 |
| E. Saugier | 11 | 5 | 1.43 |