Title
Scheduling of Iterative Algorithms on FPGA with Pipelined Arithmetic Unit
Abstract
This paper presents a scheduling technique for a libraryof arithmetic logarithmic modules for FPGA illustrated ona RLS filter for active noise cancellation. The problem underassumption is to find an optimal periodic cyclic schedulesatisfying the timing constraints. The approach is basedon a transformation to monoprocessor cyclic schedulingwith precedence delays. We prove that this problem is NP-hard and we suggest a solution based on Integer Linear Programming that allows to minimize completion time. Finallyexperimental results of optimized RLS filter are shown.
Year
DOI
Venue
2004
10.1109/RTTAS.2004.1317287
IEEE Real-Time and Embedded Technology and Applications Symposium
Keywords
Field
DocType
ona rls filter,finallyexperimental result,pipelined arithmetic unit,libraryof arithmetic logarithmic module,completion time,problem underassumption,cyclic scheduling,fpga.,integer linear programming,active noise cancellation,optimal periodic cyclic,iterative algorithms,monopro- cessor,optimized rls filter,cyclic schedulingwith precedence delay,iterative algorithm,integer programming,noise cancellation,fpga,arithmetic,computational complexity,parallel algorithms,satisfiability,linear programming,field programmable gate arrays,active noise control,np hard problem,active filters
Constraint satisfaction,Active filter,Scheduling (computing),Iterative method,Computer science,Parallel algorithm,Arithmetic,Algorithm,Real-time computing,Integer programming,Linear programming,Computational complexity theory
Conference
ISBN
Citations 
PageRank 
0-7695-2148-7
8
0.55
References 
Authors
10
3
Name
Order
Citations
PageRank
sůcha přemysl17413.96
Zdenek Pohl2568.11
Zdenek Hanzalek391.60