Name
Abstract | ||
|---|---|---|
VHDL programs are often tested by means of simulations, relying on test benches written intuitively. In this paper, we propose a formal approach to construct test benches from system specification. To consider the real-time properties of VHDL programs, we first transform them to timed automata and then perform model checking against the properties designated from the specification. Counterexamples returned from the model checker serve as a basis of test cases, i.e. they are used to form a test bench. The approach is demonstrated and complemented by a simple case study. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/SSIRI-C.2010.22 | Secure Software Integration and Reliability Improvement Companion |
Keywords | Field | DocType |
model checker,system specification,model checking,simple case study,vhdl program,synthesizable vhdl programs,towards test case generation,real-time property,formal approach,test case,test bench,real time,automata,computational modeling,radiation detectors,semantics,field programmable gate arrays,hardware description languages,formal specification | Model checking,Programming language,Program transformation,Test bench,Computer science,Formal specification,Real-time computing,Test case,VHDL,System requirements specification,Hardware description language | Conference |
ISBN | Citations | PageRank |
978-1-4244-7644-2 | 1 | 0.36 |
References | Authors | |
8 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tolga Ayav | 1 | 27 | 5.97 |
| Tugkan Tuglular | 2 | 27 | 12.51 |
| Fevzi Belli | 3 | 42 | 10.02 |