Paper Info
Title
Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000
Abstract
Providing customized memory architectures is key for achieving high-performance with reconfigurable accelerators. Since reconfigurable computers provide limited possibilities for customizing the organization of external memory, a specific challenge is to make use of the existing memory layout in a flexible, yet efficient way. In this paper we build on IMORC, our architectural template and on-chip network for creating reconfigurable accelerators, and discuss its infrastructure for accessing memory. We characterize the IMORC communication bandwidth on the XtremeData XD1000 reconfigurable computer. Based on this characterization, we present a z-buffer compositing accelerator which is able to double the frame-rate of a parallel renderer.
Year
DOI
Venue
2009
10.1109/ReConFig.2009.32
Quintana Roo
Keywords
Field
DocType
reconfigurable accelerator design,xtremedata xd1000 reconfigurable computer,reconfigurable accelerator,communication performance characterization,existing memory layout,architectural template,external memory,imorc communication bandwidth,accessing memory,limited possibility,reconfigurable computer,customized memory architecture,chip,system on a chip,reconfigurable computing,field programmable gate arrays,acceleration,parallel rendering,network on chip,bandwidth,memory management
Computer architecture,System on a chip,Computer science,Parallel computing,Field-programmable gate array,Network on a chip,Bandwidth (signal processing),Memory management,Rendering (computer graphics),Compositing,Embedded system,Auxiliary memory
Conference
ISBN
Citations 
PageRank 
978-0-7695-3917-1
2
0.38
References 
Authors
8
4
Name
Order
Citations
PageRank
Tobias Schumacher1213.30
Tim Süβ230.74
Christian Plessl329735.98
Marco Platzner41188116.17