Title
An Area And Energy Efficient Half-Row-Paralleled Layer Ldpc Decoder For The 802.11ad Standard
Abstract
Multi-gigabit LDPC decoders are demanded by standards such as IEEE 802.11ad and IEEE 802.15.3c. In order to achieve high throughput, most published multi-gigabit designs use row-paralleled architecture. In this paper, we proposed a half-row paralleled LDPC decoder with half layer level pipeline and single permutation network for the 802.11ad standard, which reduces the hardware resources almost by half compared to the state-of-the-art row-paralleled LDPC decoder, achieving a good trade-off between energy efficiency and area efficiency. The decoder achieves a throughput of 5.6 Gbps and consumes only 99 mW for the highest coding rate 13/16 at 5 iterations, working at 500 MHz by using 40nm G technology, yielding an energy efficiency of 3.53 pJ/bit/iteration and area efficiency of 35 Gbps/sqmm.
Year
DOI
Venue
2013
10.1109/SiPS.2013.6674490
2013 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS (SIPS)
Keywords
Field
DocType
802.11ad, LDPC, multi-gigabit communication, layer decoding
Energy conservation,Code rate,Computer science,Efficient energy use,Low-density parity-check code,Permutation,Real-time computing,Soft-decision decoder,Throughput,Decoding methods
Conference
ISSN
Citations 
PageRank 
2162-3562
6
0.60
References 
Authors
8
8
Name
Order
Citations
PageRank
Meng Li1113.07
Frederik Naessens2577.63
Peter Debacker3329.04
Praveen Raghavan430847.48
Claude Desset593184.11
Min Li616023.21
Antoine Dejonghe730930.25
Liesbet Van Der Perre81013108.24