Name
Abstract | ||
|---|---|---|
As the increasing number of buses in multi-core SoC designs, bus planning problems become a dominant factor in determining the chip performance. To cope with these issues, it is desirable to consider them in the early floorplanning stage. Recently, many bus-driven floorplanners have been proposed in the literature. However, these proposed algorithms only consider the bus planning problem without the thermal effect. As a result, there are hotspots, which result in high chip temperature, on the chip. In this paper, a thermal-driven bus-driven floorplanning algorithm is proposed to separate hotspots during the perturbation stage and to keep buses away from hotspots during the routing stage. To avoid time-consuming thermal simulations, the superposition of thermal profiles, which are the thermal distribution of each module, is adopted to efficiently estimate the module temperature. Compared with the state-of-the-art bus-driven floorplanner, experimental results demonstrate that the proposed algorithm can effectively separate hotspots and reduce the chip temperature. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1016/j.vlsi.2012.11.002 | Integration |
Keywords | Field | DocType |
bus-driven floorplanning,chip performance,separate hotspots,high chip temperature,thermal profile,bus planning problem,thermal consideration,time-consuming thermal simulation,thermal effect,chip temperature,thermal distribution,proposed algorithm,cad,physical design | CAD,Superposition principle,Thermal,Computer science,Hotspot (geology),Chip,Electronic engineering,Real-time computing,Physical design,Thermal distribution,Floorplan | Journal |
Volume | Issue | ISSN |
46 | 4 | 0167-9260 |
Citations | PageRank | References |
2 | 0.37 | 20 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Po-Hsun Wu | 1 | 52 | 6.05 |
| Tsung-Yi Ho | 2 | 1061 | 95.20 |