Name
Abstract | ||
|---|---|---|
This paper presents a novel 1-out-of-n checker that, compared to the other implementations up to now presented, features the advantages of: (i) satisfying the TSC or SCD property with respect to all possible internal faults representative of realistic failures; (ii) presenting a single output line; (iii) requiring significantly lower area overhead |
Year | DOI | Venue |
|---|---|---|
1998 | 10.1109/DATE.1998.655999 | Paris |
Keywords | Field | DocType |
possible internal faults representative,realistic failure,scd property,novel 1-out-of-n checker,single output line,lower area overhead,1-out-of-n code checker,telephony,decoding,satisfiability,logic circuits,computer applications,testing | Logic gate,Logic testing,Computer science,Implementation,Real-time computing,Computer errors,Computer Applications,Aerospace electronics,Decoding methods,Telephony | Conference |
ISBN | Citations | PageRank |
0-8186-8359-7 | 2 | 0.41 |
References | Authors | |
5 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| C. Metra | 1 | 373 | 39.73 |
| M. Favalli | 2 | 295 | 42.09 |
| B. Ricco | 3 | 136 | 24.67 |