Name
Abstract | ||
|---|---|---|
Two novel CMOS circuit designs implementing floating resistors are introduced, using the structure of a two-transistor CMOS bilateral linear resistor in the first configuration and two two-transistor CMOS bilateral linear resistors and cascode current mirrors in the second configuration. Linearity is achieved through nonlinearity cancellation via current mirrors over an applied range of +/-5V. PSpice simulation results using parameters of MOSIS transistors are presented to verify the theory. These floating resistors can be used for coupling weights in VLSI neural-type cell arrays. |
Year | DOI | Venue |
|---|---|---|
1998 | 10.1142/S0218126698000353 | JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS |
Field | DocType | Volume |
Coupling,Current mirror,Computer science,Cascode,Linearity,Electronic engineering,CMOS,Resistor,Transistor,Electrical engineering,Very-large-scale integration | Journal | 8 |
Issue | ISSN | Citations |
5-6 | 0218-1266 | 0 |
PageRank | References | Authors |
0.34 | 1 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Louiza Sellami | 1 | 3 | 2.11 |
| S. K. Singh | 2 | 35 | 6.95 |
| Robert W. Newcomb | 3 | 5 | 2.60 |
| A. Rasmussen | 4 | 0 | 0.34 |
| Mona E. Zaghloul | 5 | 73 | 19.65 |