Paper Info
Title
Low-Complexity Parallel QPP Interleaver Based on Permutation Patterns
Abstract
In this brief, we present how parallel-interleaved addresses generated by a quadratic permutation polynomial (QPP) interleaver are related to each other and propose a low-complexity parallel QPP interleaver based on the relationship. While a conventional parallel turbo decoder employs a number of interleavers as many as the parallel factor, the proposed method, which benefits from the arithmetic relationship denoted as the permutation pattern (PP), supports the parallel interleaving using only a single interleaver, resulting in a notable reduction of complexity. The strength of the proposed method stems from the fact that the PP is fully determined by only the decoding parameters, such as block size, parallel factor, and QPP coefficients. Experiment results on the Long Term Evolution turbo codes show that the proposed interleaver can significantly reduce the hardware complexity compared with conventional implementations.
Year
DOI
Venue
2013
10.1109/TCSII.2013.2240911
IEEE Trans. on Circuits and Systems
Keywords
Field
DocType
turbo codes,turbo decoder,low complexity parallel qpp interleaver,hardware complexity,parallel interleaving,block size,parallel architecture,quadratic permutation polynomial interleaver,long term evolution turbo codes,permutation patterns,long term evolution,parallel turbo decoder,parallel interleaved addresses,quadratic permutation polynomial (qpp) interleaver,arithmetic relationship,interleaved codes,permutation pattern (pp),decoding,logic gates,memory management,hardware
Block size,Permutation,Turbo code,Algorithm,Quadratic equation,Theoretical computer science,Electronic engineering,Permutation pattern,Decoding methods,Mathematics,Permutation polynomial,Interleaving
Journal
Volume
Issue
ISSN
60
3
1549-7747
Citations 
PageRank 
References 
2
0.38
9
Authors
3
Name
Order
Citations
PageRank
Bongjin Kim16214.14
Injae Yoo2275.26
In-Cheol Park3888124.36