Name
Abstract | ||
|---|---|---|
Dynamic reconfiguration using FPGAs has been demonstrated to be highly efficient in different application domains. However little has been explored in the avionic communication domain, where halting the system during runtime for changing the hardware is non-trivial. In this paper we present a runtime reconfigurable architecture using I/O Intellectual Property (IP) cores, used in avionic applications. The system provides a modular I/O interface for communication, using an FPGA Mezzanine Card (FMC). User application can dynamically install and execute the necessary hardware for communication with external avionic sub-systems using FMC. The system thus provides a highly modular and cost effective autonomous solution for an embedded avionic communication system using Dynamic Partial Reconfiguration (DPR). The above described solution has been tested using a Xilinx ML605 prototyping board providing a software interface with a Xilinx Microblaze processor core. The architecture has been evaluated with the JPEG application in terms of area utilization, reconfiguration latency and execution time. The reconfiguration latency can be hidden totally in many cases. While in certain others, the overhead of reconfiguration can be justified by the reduction in the resource utilization. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/ReConFig.2012.6416741 | ReConFig |
Keywords | Field | DocType |
execution time,logic circuits,ml605 prototyping board,embedded avionic communication system,intensive signal processing applications,microprocessor chips,resource utilization reduction,external avionic subsystems,aerospace computing,aircraft communication,fpga mezzanine module,fpga mezzanine card,area utilization,reconfigurable architectures,software interface,avionic ip cores,reconfiguration latency,avionic application,cost effective autonomous solution,runtime reconfigurable architecture,software prototyping,fmc,industrial property,modular i/o interface,dynamic partial reconfiguration,avionic communication domain,ip cores,peripheral interfaces,modular and reconfigurable i/os,xilinx microblaze processor core,jpeg application,field programmable gate arrays,i/o intellectual property cores,avionics | MicroBlaze,FPGA Mezzanine Card,Computer science,Parallel computing,Software prototyping,Field-programmable gate array,Input/output,Real-time computing,Modular design,Multi-core processor,Control reconfiguration,Embedded system | Conference |
ISBN | Citations | PageRank |
978-1-4673-2919-4 | 8 | 0.69 |
References | Authors | |
7 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Venkatasubramanian Viswanathan | 1 | 15 | 2.72 |
| Benjamin Nakache | 2 | 10 | 1.49 |
| Rabie Ben Atitallah | 3 | 173 | 20.23 |
| Maurice Nakache | 4 | 10 | 1.49 |
| Jean-luc Dekeyser | 5 | 433 | 53.54 |