Name
Abstract | ||
|---|---|---|
The reusing of Intellectual Property cores has been an alternative to the increasing gap between design productivity and chip complexity of emerging System-on-chip (SoC) designs. But the design of IP-cores has its own challenges like portability, reusability, standards interfaces, well-defined and useful documentation, easy to integration and so on. All these characteristics together make the design of an IP-core a complex task and in this way teaching this discipline has became a new challenge for educators. In this paper we present an experience about how the utilization of a well-defined development process can be used to facilitate and speed-up students learning. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1109/MSE.2005.38 | MSE |
Keywords | Field | DocType |
well-defined development process,standards interface,own challenge,complex task,intellectual property core,design productivity,new challenge,speed-up student,chip complexity,teach ip-core development,increasing gap,design methodology,system on chip,field programmable gate arrays,informatics,soc,system on a chip,integrated circuit design,chip,productivity,prototypes,intellectual property,teaching,documentation,development process | System on a chip,Software engineering,Reuse,Design methods,Integrated circuit design,Software portability,Engineering,Intellectual property,Documentation,Computer engineering,Reusability | Conference |
ISBN | Citations | PageRank |
0-7695-2374-9 | 0 | 0.34 |
References | Authors | |
0 | 6 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Marilia Lima | 1 | 0 | 0.68 |
| Andre Aziz | 2 | 4 | 1.19 |
| Diogo Alves | 3 | 0 | 0.34 |
| Patricia Lira | 4 | 0 | 0.34 |
| Vitor Schwambach | 5 | 0 | 0.34 |
| Edna Barros | 6 | 145 | 13.04 |