Name
Abstract | ||
|---|---|---|
This paper presents a design of a 6-bit 2.704Gsamples/s D/A converter (DAC) for DS-CDMA UWB transceivers. The proposed DAC was designed with a current steering segmented 4+2 architecture for high frequency sampling rate. For low glitches, optimized deglitch circuit is adopted for the selection of current sources. The measured integral nonlinearity (INL) is -0.081 LSB and the measured differential nonlinearity (DNL) is -0.065 LSB. The DAC implemented in a 0.13mum CMOS technology shows s spurious free dynamic range (SFDR) of 41dB at f signal 300Mhz. The prototype DAC consumes 28mW for a Nyquist sinusoidal output signal at a 2.704Gsamples/s. The chip has an active area of 0.76mm2 |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/APCCAS.2006.342441 | APCCAS |
Keywords | Field | DocType |
spurious free dynamic range,cmos integrated circuits,transceivers,uwb,ultra wideband communication,integral nonlinearity,spread spectrum communication,cmos technology,code division multiple access,uwb transceivers,dac,ds-cdma,differential nonlinearity,deglitch,cmos,0.13 micron,digital-analogue conversion,high frequency,chip | Integral nonlinearity,Differential nonlinearity,Computer science,Sampling (signal processing),CMOS,Electronic engineering,Chip,Spurious-free dynamic range,Electrical engineering,Least significant bit,Spread spectrum | Conference |
ISBN | Citations | PageRank |
1-4244-0387-1 | 4 | 1.09 |
References | Authors | |
0 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jae-jin Jung | 1 | 4 | 1.09 |
| Bong-hyuck Park | 2 | 5 | 1.85 |
| Sang-seong Choi | 3 | 5 | 1.85 |
| Shin-il Lim | 4 | 8 | 10.10 |
| Suki Kim | 5 | 138 | 39.60 |