A high performance full pipelined arquitecture of MLP Neural Networks in FPGA. - Citegraph

Paper Info

Title
A high performance full pipelined arquitecture of MLP Neural Networks in FPGA.

Year	DOI	Venue
2010	10.1109/ICECS.2010.5724619	ICECS
Keywords	Field	DocType
field programmable gate arrays,fpga,iris,artificial neural network,hardware architecture,multilayer perceptron,adders	Architecture,Adder,% area reduction,Computer science,Field-programmable gate array,Electronic engineering,Multilayer perceptron,Interconnection,Artificial neural network,Hardware architecture	Conference
Citations	PageRank	References
2	0.38	5
Authors
2

Authors (2 rows)

Cited by (2 rows)

References (5 rows)

Name	Order	Citations	PageRank
Antonyus Pyetro do Amaral Ferreira	1	8	3.21
Edna Natividade da Silva Barros	2	59	11.11

1