Name
Abstract | ||
|---|---|---|
This letter presents point diffusion clock network (PDCN) with local clock tree synthesis (CTS) scheme. The clock network is implemented with ten times wider metal line space than typical mesh networks for low power and utilized to nine times smaller area CTS execution for minimized clock skew amount. The measurement results show that skew amount of PDCN with local CTS is reduced to 36% and latency is shrunk to 45% of the amount in a 4.81 mm(2) CortexA-8 core with 65 nm Samsung process. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1093/ietele/e91-c.11.1832 | IEICE TRANSACTIONS ON ELECTRONICS |
Keywords | Field | DocType |
clock network, skew, latency, low power | Clock gating,Mesh networking,Clock network,Frequency synthesizer,Electronic engineering,Clock skew,Skew,Engineering,CPU multiplier,Low-power electronics | Journal |
Volume | Issue | ISSN |
E91C | 11 | 1745-1353 |
Citations | PageRank | References |
0 | 0.34 | 3 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Gunok Jung | 1 | 33 | 5.96 |
| Chunghee Kim | 2 | 49 | 7.50 |
| Kyoungkuk Chae | 3 | 0 | 0.34 |
| Gi-Ho Park | 4 | 76 | 17.47 |
| Sung Bae Park | 5 | 4 | 1.67 |