Paper Info
Title
A Dual-Channel 6b 1gs/S 0.18um Cmos Adc For Ultra Wide-Band Communication Systems
Abstract
This work proposes a dual-channel 6b 1GS/s ADC for ultra wide-band communication system applications. The proposed ADC based on a 6b interpolated flash architecture employs wide-band open-loop track-and-hold amplifiers, comparators with a wide-range differential difference preamplifier, latches with reduced kickback noise, on-chip CMOS references, and digital bubble code correction circuits to optimize power, chip area, and accuracy at 1GS/s. The ADC implemented in a 0.18mn 1P6M CMOS technology shows a signal-to-noise-and-distortion ratio of 30dB and a spurious-free dynamic range of 39dB at 1GS/s. The measured differential and integral nonlinearities of the prototype ADC are within 1.00LSB and 1.25LSB, respectively. The dual-channel ADC has an active area of 4.0mm(2) and consumes 594mW at 1GS/s and 1.8V.
Year
DOI
Venue
2006
10.1109/APCCAS.2006.342420
2006 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS
Keywords
DocType
Citations 
ADC, CMOS, flash, kickback, ultra wide band
Conference
1
PageRank 
References 
Authors
0.40
3
8
Name
Order
Citations
PageRank
Young-jae Cho1315.99
Kyung-Hoon Lee27115.77
Hee-Cheol Choi32610.68
Young-Ju Kim426829.56
Kyoung-Jun Moon5153.20
Seunghoon Lee624461.57
Seok-Bong Hyun7242.73
Seong-su Park820.84