Name
Abstract | ||
|---|---|---|
Genetic-algorithm based techniques have been used to successfully calibrate both analogue and digital VLSI chips. This paper investigates the potential of applying the developed techniques to a generic high-speed digital system, which comprises an analogue-to-digital converter and digital logic integrated on a single chip.It is concluded that evolvable calibration techniques are most likely to be applied to VLSI design where the actual value of a variable is critical rather than the more common instance of the variable having to be greater than a given value or the quantity of interest is the ratio of two matched components. Probably the best example of this is delay. As clock frequencies approach 1GHz, variation of buffer delay and clock skew become increasingly important. |
Year | DOI | Venue |
|---|---|---|
2000 | 10.1109/EH.2000.869350 | Evolvable Hardware |
Keywords | Field | DocType |
digital vlsi chip,best example,clock skew,clock frequencies approach,actual value,generic high-speed digital system,digital logic,analogue-to-digital converter,buffer delay,vlsi design,evolutionary approach,ghz digital systems,calibration,chip,genetic algorithms,very large scale integration,vlsi,logic,circuits,genetic algorithm,hardware | Computer science,Electronic engineering,Chip,Clock skew,Boolean algebra,Digital clock manager,Electronic circuit,Very-large-scale integration,Genetic algorithm,Calibration | Conference |
ISBN | Citations | PageRank |
0-7695-0762-X | 0 | 0.34 |
References | Authors | |
3 | 7 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Neil Marston | 1 | 2 | 0.75 |
| Eiichi Takahashi | 2 | 131 | 16.54 |
| Masahiro Murakawa | 3 | 214 | 37.45 |
| Yuji Kasai | 4 | 19 | 4.12 |
| Tetsuya Higuchi | 5 | 905 | 142.80 |
| Toshio Adachi | 6 | 25 | 5.07 |
| Kaoru Takasuka | 7 | 49 | 9.42 |