Paper Info
Title
Automatic Resource Scheduling with Latency Hiding for Parallel Stencil Applications on GPGPU Clusters
Abstract
Overlapping computations and communication is a key to accelerating stencil applications on parallel computers, especially for GPU clusters. However, such programming is a time-consuming part of the stencil application development. To address this problem, we developed an automatic code generation tool to produce a parallel stencil application with latency hiding automatically from its dataflow model. With this tool, users visually construct the workflows of stencil applications in a dataflow programming model. Our dataflow compiler determines a data decomposition policy for each application, and generates source code that overlaps the stencil computations and communication (MPI and PCIe). We demonstrate two types of overlapping models, a CPU-GPU hybrid execution model and a GPU-only model. We use a CFD benchmark computing 19-point 3D stencils to evaluate our scheduling performance, which results in 1.45 TFLOPS in single precision on a cluster with 64 Tesla C1060 GPUs.
Year
DOI
Venue
2012
10.1109/IPDPS.2012.57
IPDPS
Keywords
Field
DocType
overlapping model,dataflow compiler,stencil application development,gpu-only model,parallel stencil application,stencil application,automatic resource scheduling,dataflow programming model,cpu-gpu hybrid execution model,stencil computation,latency hiding,gpgpu clusters,dataflow model,parallel stencil applications,partial differential equations,computational modeling,hardware,parallel processing,kernel
Computer science,Source code,Stencil,Parallel computing,Stencil code,Code generation,Compiler,Dataflow,Execution model,Dataflow programming,Distributed computing
Conference
ISSN
Citations 
PageRank 
1530-2075
1
0.36
References 
Authors
0
6
Name
Order
Citations
PageRank
Kumiko Maeda11149.36
Masana Murase2173.59
Munehiro Doi3112.82
Hideaki Komatsu441034.00
Shigeho Noda571.88
Ryutaro Himeno64313.10