Title
Spikes monitors for FPGAs, an experimental comparative study
Abstract
In this paper we present and analyze two VHDL components for monitoring internal activity of spikes fired by silicon neurons inside FPGAs. These spikes monitors encode each spike according to the Address-Event Representation, sending them through a time multiplexed digital bus as discrete events, using different strategies. In order to study and analyze their behavior we have designed an experimental scenario, where diverse AER systems have been used to stimulate the spikes monitors and collect the output AER events, for later analysis. We have applied a battery of tests on both monitors in order to measure diverse features such as maximum spike load and AER event loss due to collisions.
Year
DOI
Venue
2013
10.1007/978-3-642-38679-4_17
IWANN (1)
Keywords
Field
DocType
maximum spike load,experimental comparative study,different strategy,diverse aer system,address-event representation,vhdl component,diverse feature,spikes monitor,output aer event,digital bus,aer event loss
ENCODE,Computer science,Field-programmable gate array,VHDL,Battery (electricity),Multiplexing,Embedded system
Conference
Volume
ISSN
Citations 
7902
0302-9743
4
PageRank 
References 
Authors
0.45
9
6