Name
Abstract | ||
|---|---|---|
This work proposes a technique to automatically obtain timing constraints for a given timed circuit to operate correctly. A designated set of delay parameters of a circuit are first set to sufficiently large bounds, and verification runs followed by failure analysis are repeated. Each verification run performs timed state space enumeration under the given delay bounds, and produces a failure trace if it exists. The failure trace is analyzed, and sufficient timing constraints to prevent the failure are obtained. Then, the delay bounds are tightened according to the timing constraints by using an ILP (Integer Linear Programming) solver. This process terminates when either some delay bounds under which no failure is detected are found or no new delay bounds to prevent the failures can be obtained. The experimental results using a naive implementation show that the proposed method can efficiently handle asynchronous benchmark circuits and nontrivial GasP circuits. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1093/ietisy/e88-d.11.2555 | IEICE Transactions |
Keywords | Field | DocType |
verification run,automatic timing,delay parameter,failure trace analysis,asynchronous benchmark circuit,new delay,nontrivial gasp circuit,failure trace,failure analysis,timing constraint,delay bound,sufficient timing constraint,timed circuits | Asynchronous communication,Trace analysis,Computer science,Circuit design,Algorithm,Integer programming,Solver,Formal methods,Electronic circuit,State space enumeration | Journal |
Volume | Issue | ISSN |
E88-D | 11 | 1745-1361 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tomoya Kitai | 1 | 12 | 1.73 |
| Tomohiro Yoneda | 2 | 353 | 41.62 |
| Chris Myers | 3 | 72 | 10.44 |