Name
Abstract | ||
|---|---|---|
In this paper, a low power and high performance three-dimensional (3-D) stacking multimedia platform called "3D-PAC" is proposed. This platform is a heterogeneous integration composed of a low power design logic layer (2D-PAC) and a reconfigurable memory tier via 3-D technology. After extensive 3-D architecture exploration with Electronic System Level (ESL) simulation, there is a 54% performance speedup compared with the former 2-D architecture for certain multimedia applications. This chip is fabricated in TSMC 90nm generic CMOS technology. The area of 2D-PAC is about 7880 x 7880 μm2 and the SRAM layer is about 3880 x 3880 μm2. Both layers are combined with 1,886 TSVs. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1145/2483028.2483117 | ACM Great Lakes Symposium on VLSI |
Keywords | Field | DocType |
multimedia platform,low power,3-d technology,low power design logic,sram layer,generic cmos technology,2-d architecture,reconfigurable memory architecture,extensive 3-d architecture exploration,certain multimedia application,high performance | Architecture,Computer science,Electronic system-level design and verification,Electronic engineering,Static random-access memory,CMOS,Chip,Multimedia,Memory architecture,Speedup,Embedded system,Stacking | Conference |
Citations | PageRank | References |
0 | 0.34 | 1 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Po-Han Huang | 1 | 4 | 1.82 |
| Huang-Lun Lin | 2 | 3 | 1.11 |
| Hsien-Ching Hsieh | 3 | 5 | 2.55 |
| Chi-Hung Lin | 4 | 217 | 34.67 |
| Shui-An Wen | 5 | 1 | 1.37 |
| Yi-Fa Sun | 6 | 3 | 2.22 |