Paper Info
Title
An Optimization Mechanism Intended for Two-Level Cache Hierarchy to Improve Energy and Performance Using the NSGAII Algorithm
Abstract
Tuning cache architectures in MPSoC platforms for embedded applications can dramatically reduce energy consumption. This paper presents a design tool for adjusting a two-level cache memory hierarchy that uses a fast non-dominated sorting algorithm (NSGAII) in order to provide decision support capabilities. It aims to reduce energy consumption and improve the performance of embedded applications. This optimization mechanism finds the best set of cache configurations (Pareto-Front) and offers support to the architecture designer in order to provide a set of non-dominated solutions for a decision maker. In our experiments, we applied the proposed mechanism to 12 different applications from the MiBench benchmark suite. Furthermore, the simulation results showed that the solutions found by our proposal are comparable to the results of other techniques and, for 67% of the analyzed cases, the efficiency of the mechanism was achieved.
Year
DOI
Venue
2008
10.1109/SBAC-PAD.2008.9
SBAC-PAD
Keywords
Field
DocType
optimization mechanism,best set,energy consumption,improve energy,decision support capability,cache configuration,two-level cache hierarchy,nsgaii algorithm,two-level cache memory hierarchy,proposed mechanism,embedded application,decision maker,cache architecture,sorting,system on chip,pareto front,sorting algorithm,decision support,cache memory,memory cache
Cache-oblivious algorithm,CPU cache,Computer science,Cache,Parallel computing,Cache algorithms,Real-time computing,Sorting,MPSoC,Energy consumption,Sorting algorithm
Conference
ISSN
Citations 
PageRank 
1550-6533
3
0.39
References 
Authors
11
5
Name
Order
Citations
PageRank
Abel Guilhermino Silva-Filho16212.94
Carmelo J. A. Bastos-Filho28118.45
Davi M. A. Falcão3111.10
F. R. Cordeiro4467.14
Rodrigo M. C. S. Castro550.80