Name
Abstract | ||
|---|---|---|
To enable statistical static timing analysis, for each cell in a digital library, a timing model that considers variations must be characterized. In this paper, we propose a dynamic method to accurately and efficiently characterize a cell's delay and output slew as a function of random mismatch variations. Based on a tight error bound for characterization using partial devices, our method sequentially performs simulations based on decreasing importance of devices and stops when the error requirement is met. Results on an industrial 32nm library demonstrate that the proposed method achieves significantly better accuracy-efficiency trade-off compared to other partial finite differencing approaches. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1145/2429384.2429419 | ICCAD |
Keywords | Field | DocType |
tight error,standard cell,digital library,timing circuits,statistical static timing analysis,partial devices,random mismatch characterization,timing model,standard cells,delay circuits,cell delay,partial device,efficient random mismatch characterization,size 32 nm,error requirement,dynamic method,cellular arrays,industrial library,partial finite differencing approach,method sequentially,error statistics,accuracy,statistical distance,finite difference methods,criticality,transistors,logic gates,sensitivity | Logic gate,Statistical static timing analysis,Computer science,Real-time computing,Electronic engineering,Finite difference method,Digital library,Criticality,Statistical distance,Transistor,Dynamic method | Conference |
ISSN | Citations | PageRank |
1092-3152 | 1 | 0.39 |
References | Authors | |
8 | 7 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Wangyang Zhang | 1 | 138 | 9.98 |
| Amith Singhee | 2 | 347 | 22.94 |
| Xiong Jinjun | 3 | 801 | 86.79 |
| Peter Habitz | 4 | 28 | 1.79 |
| Amol Joshi | 5 | 1 | 0.73 |
| Chandu Visweswariah | 6 | 615 | 60.90 |
| James Sundquist | 7 | 1 | 0.39 |