Paper Info
Title
An efficient TLM/T modeling and simulation environment based on conservative parallel discrete event principles
Abstract
The paper presents an innovative simulation scheme to speed-up simulations of multi-clusters multi-processors SoCs at the TLM/T (Transaction Level Model with Time) abstraction level. The hardware components of the SoC architecture are written in standard SystemC. The goal is to describe the dynamic behavior of a given software application running on a given hardware architecture (including the dynamic contention in the interconnect and the cache effects), in order to provide the system designer with the same reliable timing information as a cycle accurate simulation, with a simulation speed similar to a TLM simulation. The key idea is to apply Parallel Discrete Event Simulation (PDES) techniques to a collection of communicating SystemC SC_THREAD. Experimental results show a simulation speedup of a factor up to 50 versus a BCA simulation (Bus Cycle Accurate), for a timing error lower than 10−3.
Year
DOI
Venue
2006
10.1109/DATE.2006.244003
DATE
Keywords
Field
DocType
simulation speedup,dynamic behavior,cycle accurate simulation,conservative parallel discrete event,systemc sc_thread,bca simulation,simulation environment,innovative simulation scheme,soc architecture,tlm simulation,dynamic contention,simulation speed,efficient tlm,computer architecture,system on chip,system design,bandwidth,discrete event simulation,hardware architecture,hardware,real time systems,application software,dynamic content,modeling and simulation
System on a chip,Computer science,Modeling and simulation,Parallel computing,Real-time computing,SystemC,Logic simulation,Abstraction layer,Speedup,Discrete event simulation,Hardware architecture
Conference
ISSN
ISBN
Citations 
1530-1591
3-9810801-0-6
26
PageRank 
References 
Authors
1.61
9
3
Name
Order
Citations
PageRank
Emmanuel Viaud1282.00
François Pêcheux212116.70
Alain Greiner363079.17