Paper Info
Title
A High-Speed Pipelined Degree-Computationless Modified Euclidean Algorithm Architecture for Reed-Solomon Decoders
Abstract
This paper presents a novel high-speed low-complexity pipelined degree-computationless modified Euclidean (pDCME) algorithm architecture for high-speed RS decoders. The pDCME algorithm allows elimination of the degree-computation so as to reduce hardware complexity and obtain high-speed processing. A high-speed RS decoder based on the pDCME algorithm has been designed and implemented with 0.13-mum CMOS standard cell technology in a supply voltage of 1.1 V. The proposed RS decoder operates at a clock frequency of 660 MHz and has a throughput of 5.3 Gb/s. The proposed architecture requires approximately 15% fewer gate counts and a simpler control logic than architectures based on the popular modified Euclidean algorithm.
Year
DOI
Venue
2008
10.1109/ISCAS.2007.378071
IEICE Transactions
Keywords
Field
DocType
reduced hardware complexity,high-speed pipelined degree-computationless,high-speed rs decoder,high-speed processing,algorithm architecture,reed-solomon decoders,euclidean algorithm architecture,reed-solomon codes,660 mhz,proposed architecture,5.3 gbit/s,clock frequency,proposed rs decoder,cmos digital integrated circuits,galois fields,modified euclidean algorithm,coprocessors,1.1 v,high-speed low-complexity pipelined degree-computationless,pdcme algorithm,cmos standard cell technology,0.13 micron,fewer gate count,popular modified euclidean algorithm,algorithm design and analysis,voltage,throughput,cmos technology,decoding,frequency,hardware
Computer science,Parallel computing,Euclidean algorithm,CMOS,Electronic engineering,Reed–Solomon error correction,Control logic,Standard cell,Throughput,Coprocessor,Clock rate
Journal
Volume
Issue
ISSN
E91-A
3
1745-1337
ISBN
Citations 
PageRank 
1-4244-0921-7
22
1.85
References 
Authors
5
4
Name
Order
Citations
PageRank
Seungbeom Lee1457.04
Hanho Lee220540.92
Jongyoon Shin3272.95
Jesoo Ko4273.96