Paper Info
Title
Design of oversampling current steering DAC with 640 MHz equivalent clock frequency
Abstract
Recent mobile communications demand high-speed and high-resolution data converters for digital signal processing (DSP) in the receiver and transceiver of the communication systems. Those applications require more than 14-bit resolution and several hundred of MHz bandwidth. In this paper, we propose a new sigma-delta parallel DAC (Digital-to-Analog Converter) structure that achieves the required accuracy with 640 MHz clock frequency. The circuit employs current steering and multi-bit solution with matching technique. The entire architecture has been verified by simulations with a 0.18 μm CMOS process (TI).
Year
DOI
Venue
2002
10.1109/ISCAS.2002.1009789
ISCAS (1)
Keywords
Field
DocType
cmos process,cmos integrated circuits,sigma-delta modulation,mobile communication,mobile communications,digital-to-analog converter structure,dsp,sigma-delta parallel dac,14 bit,high-speed integrated circuits,640 mhz,high-speed data converters,high-resolution data converters,oversampling current steering dac,multi-bit dac,0.18 micron,digital signal processing,digital-analogue conversion,transceivers,circuits,delta sigma modulation,bandwidth,high resolution
Digital signal processing,Transceiver,Oversampling,Computer science,CMOS,Delta-sigma modulation,Electronic engineering,Bandwidth (signal processing),Electronic circuit,Electrical engineering,Clock rate
Conference
Volume
Citations 
PageRank 
1
1
0.37
References 
Authors
1
2
Name
Order
Citations
PageRank
Yunyoung Choi1274.42
Franco Maloberti2686144.70