Paper Info
Title
Multi-layer parallel decoding algorithm and vlsi architecture for quasi-cyclic LDPC codes
Abstract
We propose a multi-layer parallel decoding algorithm and VLSI architecture for decoding of structured quasi-cyclic low-density parity-check codes. In the conventional layered decoding algorithm, the block-rows of the parity check matrix are processed sequentially, or layer after layer. The maximum number of rows that can be simultaneously processed by the conventional layered decoder is limited to the sub-matrix size. To remove this limitation and support layer-level parallelism, we extend the conventional layered decoding algorithm and architecture to enable simultaneously processing of multiple (K) layers of a parity check matrix, which will lead to a roughly K-fold throughput increase. As a case study, we have designed a double-layer parallel LDPC decoder for the IEEE 802.11n standard. The decoder was synthesized for a TSMC 45-nm CMOS technology. With a synthesis area of 0.81 mm2 and a maximum clock frequency of 815 MHz, the decoder achieves a maximum throughput of 3.0 Gbps at 15 iterations.
Year
DOI
Venue
2011
10.1109/ISCAS.2011.5937928
ISCAS
Keywords
Field
DocType
cmos integrated circuits,multilayer parallel decoding algorithm,cyclic codes,vlsi architecture,quasi-cyclic ldpc codes,cmos technology,tsmc,ieee 802.11n standard,vlsi,layered decoder,quasi-cyclic low-density parity-check codes,sub-matrix size,parity check matrix,wireless lan,ldpc code,registers,decoding,double layer,parallel processing,very large scale integration,throughput
Sequential decoding,Parity-check matrix,Low-density parity-check code,Computer science,Parallel computing,Algorithm,Electronic engineering,Soft-decision decoder,Decoding methods,Throughput,Very-large-scale integration,Clock rate
Conference
ISSN
ISBN
Citations 
0271-4302 E-ISBN : 978-1-4244-9472-9
978-1-4244-9472-9
17
PageRank 
References 
Authors
0.83
5
3
Name
Order
Citations
PageRank
Yang Sun137824.59
Guohui Wang2108860.78
Joseph R. Cavallaro31175115.35