Paper Info
Title
Parallelization strategies for the points of interests algorithm on the cell processor
Abstract
The Cell processor is a typical example of a heterogeneous multiprocessor-on-chip architecture that uses several levels of parallelism to deliver high performance. Closing the gap between peak performance and sustained performance is the challenge for software tool developers and the application developers. Image processing and media applications are typical "main stream" applications. In this paper, we use the Harris algorithm for detection of points of interest (PoI) in an image as a benchmark to compare the performance of several parallel schemes on a Cell processor. The impact of the DMA controlled data transfers and the synchronizations between SPEs explains the differences between the performance of the different parallelization schemes. These results will be used to design a tool for an efficient mapping of image processing applications on multi-core architectures.
Year
DOI
Venue
2007
10.1007/978-3-540-74742-0_12
ISPA
Keywords
Field
DocType
application developer,image processing application,cell processor,typical example,interests algorithm,image processing,software tool developer,high performance,parallelization strategy,harris algorithm,sustained performance,peak performance,application development,chip,point of interest,data transfer
Software tool,Architecture,Computer science,Parallel computing,Algorithm,Image processing,Real-time computing,Point of interest,Distributed computing
Conference
Volume
ISSN
ISBN
4742
0302-9743
3-540-74741-9
Citations 
PageRank 
References 
4
0.46
6
Authors
4
Name
Order
Citations
PageRank
Tarik Saidani1182.54
Lionel Lacassagne212723.17
Samir Bouaziz33613.18
Taj Muhammad Khan440.46